Method for fabricating a semiconductor package

ABSTRACT

A method for fabricating a semiconductor package includes forming a release layer on a first carrier substrate. An etch stop layer is formed on the release layer. A first redistribution layer is formed on the etch stop layer and includes a plurality of first wires and a first insulation layer surrounding the plurality of first wires. A first semiconductor chip is formed on the first redistribution layer. A solder ball is formed between the first redistribution layer and the first semiconductor chip. A second carrier substrate is formed on the first semiconductor chip. The first carrier substrate, the release layer, and the etch stop layer are removed. The second carrier substrate is removed.

This application claims priority under 35 U.S.C. § 119 to Korean PatentApplication No. 10-2019-0099323, filed on Aug. 14, 2019 in the KoreanIntellectual Property Office (KIPO), the disclosure of which isincorporated by reference in its entirety herein.

1. TECHNICAL FIELD

The present disclosure relates to a method for fabricating asemiconductor package.

2. DISCUSSION OF RELATED ART

The sizes of semiconductor chips and semiconductor packages haveincreased in recent years as the consumer demand for high-performanceelectronic devices has increased. However, the thicknesses ofsemiconductor packages have decreased due to recent trends towardsrelatively thin electronic devices.

Semiconductor packages have been developed to provide improvedperformance to satisfy the demands for multi functionality,high-capacitance, and miniaturization. For example, a plurality ofsemiconductor chips may be integrated into a single semiconductorpackage, and thus, high-capacitance and multi functionality may beachieved while significantly reducing the size of the semiconductorpackage.

SUMMARY

An object to be achieved by the present inventive concepts is to providea method for fabricating a semiconductor package, which forms an etchstop layer including metal between a carrier substrate and aredistribution layer, and prevents the redistribution layer from beingdamaged in a debonding process of the carrier substrate.

According to an exemplary embodiment of the present inventive concepts,a method for fabricating a semiconductor package includes forming arelease layer on a first carrier substrate. An etch stop layer is formedon the release layer. A first redistribution layer is formed on the etchstop layer and includes a plurality of first wires and a firstinsulation layer surrounding the plurality of first wires. A firstsemiconductor chip is formed on the first redistribution layer. A solderball is formed between the first redistribution layer and the firstsemiconductor chip. A second carrier substrate is formed on the firstsemiconductor chip. The first carrier substrate, the release layer, andthe etch stop layer are removed. The second carrier substrate isremoved.

According to an exemplary embodiment of the present inventive concepts,a method for fabricating a semiconductor package includes forming arelease layer on a first carrier substrate. An etch stop layercomprising metal is formed on the release layer. A first redistributionlayer is formed on the etch stop layer. The first redistribution layerincludes a plurality of first wires and a first insulation layersurrounding the plurality of first wires. A first semiconductor chip isformed on the first redistribution layer. A solder ball is formedbetween the first redistribution layer and the first semiconductor chip.A molding layer is formed that covers the first semiconductor chip. Thefirst carrier substrate, the release layer, and the etch stop layer areremoved. The release layer and the first insulation layer comprise asame material.

According to an exemplary embodiment of the present inventive concepts,a method for fabricating a semiconductor package includes forming arelease layer on a first carrier substrate. An etch stop layercomprising metal is formed on the release layer. A first redistributionlayer is formed on the etch stop layer. The first redistribution layerincludes a plurality of first wires and a first insulation layersurrounding the plurality of first wires. A first semiconductor chip isformed on the first redistribution layer. A solder ball is formedbetween the first redistribution layer and the first semiconductor chip.A molding layer is formed that covers the first semiconductor chip. Asecond carrier substrate is formed on the molding layer. The firstcarrier substrate, the release layer, and the etch stop layer areremoved. The second carrier substrate is removed. The release layer andthe first insulation layer comprise a same material.

The objectives that are intended to be addressed by the presentinventive concepts are not limited to those mentioned above, and otherobjectives that are not mentioned above may be clearly understood tothose skilled in the art based on the description provided below.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, features and advantages of the presentinventive concepts will become more apparent to those of ordinary skillin the art by describing in detail exemplary embodiments thereof withreference to the accompanying drawings, in which:

FIG. 1 is a cross-sectional view of a semiconductor package according toan exemplary embodiment of the present inventive concepts;

FIGS. 2 to 8 are cross-sectional views illustrating a method forfabricating a semiconductor package according to exemplary embodimentsof the present inventive concepts;

FIGS. 9 and 10 are cross-sectional views illustrating a method forfabricating a semiconductor package according to other exemplaryembodiments of the present inventive concepts;

FIGS. 11 to 14 are cross-sectional views illustrating a method forfabricating a semiconductor package according to exemplary embodimentsof the present inventive concepts;

FIGS. 15 to 18 are cross-sectional views illustrating a method forfabricating a semiconductor package according to some other exemplaryembodiments of the present inventive concepts;

FIG. 19 is a cross-sectional view of a semiconductor package accordingto an exemplary embodiment of the present inventive concepts; and

FIG. 20 is a cross-sectional view of a semiconductor package accordingto an exemplary embodiment of the present inventive concepts.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

According to some exemplary embodiments of the present inventiveconcepts, a method for fabricating a semiconductor package may includefabricating a fan-out package. For example, a semiconductor chip may beformed on a redistribution layer. The semiconductor chip may beelectrically connected to an external device through the redistributionlayer and a solder ball formed on the redistribution layer. However,exemplary embodiments of the present inventive concepts are not limitedthereto. In the present Specification, the terms “formed on” and“disposed on” mean that an element is formed either directly on anotherelement or the element is formed indirectly thereon with one or moreintervening elements/layers present. The term “formed directly on” meansthat an element is formed directly on another element with nointervening elements/layers present.

Hereinafter, a semiconductor package fabricated by a method forfabricating a semiconductor package according to some exemplaryembodiments of the present inventive concepts will be described withreference to FIG. 1.

FIG. 1 is a cross-sectional view provided to explain a semiconductorpackage fabricated by a method for fabricating a semiconductor packageaccording to an exemplary embodiment of the present inventive concepts.

The semiconductor package may include a first redistribution layer 130,a first semiconductor chip 140, a first underfill material 141, a firstmolding layer 145, a first solder ball 151, and a second solder ball152.

The first redistribution layer 130 may include a plurality of firstwires 131, a first redistribution via 132, and a first insulation layer133.

As shown in the exemplary embodiment of FIG. 1, the plurality of firstwires 131 may include a plurality of wires spaced apart from one anotherin a horizontal direction (e.g., the X direction). In addition, theplurality of first wires 131 may also include a plurality of wiresspaced apart from one another in a vertical direction (e.g., the Ydirection). For example, the plurality of first wires 131 may include aplurality of wires spaced apart from one another in the horizontaldirection and formed on different levels. As shown in the exemplaryembodiment of FIG. 1, the plurality of first wires 131 may include firstwires 131 that are horizontally arranged and formed on three differentlevels. However, exemplary embodiments of the present inventive conceptsare not limited thereto. A plurality of first redistribution vias 132are formed on first wires 131 on each level and extend vertically (e.g.,in the Y direction) to connect first wires 131 to each other ondifferent levels.

Each of the wires included in the plurality of first wires 131 mayinclude a conductive material. For example, each of the wires includedin the plurality of first wires 131 may include copper (Cu). In anexemplary embodiment, each of the wires included in the plurality offirst wires 131 may include at least one compound selected from carbon(C), silver (Ag), cobalt (Co), tantalum (Ta), indium (In), tin (Sn),zinc (Zn), manganese (Mn), titanium (Ti), magnesium (Mg), chromium (Cr),germanium (Ge), strontium (Sr), platinum (Pt), magnesium (Mg), aluminum(Al), and zirconium (Zr).

The first redistribution via 132 may electrically connect between theplurality of first wires 131 formed on different levels. The firstredistribution via 132 may include a conductive material. For example,in an exemplary embodiment, the first redistribution via 132 may includea same material as the material of the plurality of first wires 131.However, exemplary embodiments of the present inventive concepts are notlimited thereto.

The first insulation layer 133 may be arranged to surround the pluralityof first wires 131 and the first redistribution via 132, respectively.

In an exemplary embodiment, the first insulation layer 133 may include aphoto imageable dielectric (PID). For example, the first insulationlayer 133 may include a photosensitive insulating material. In anexemplary embodiment, the first insulation layer 133 may include atleast one compound selected from epoxy and polyimide. However, exemplaryembodiments of the present inventive concepts are not limited thereto.

In an exemplary embodiment, the first semiconductor chip 140 may be alogic chip or a memory chip. In an embodiment in which the firstsemiconductor chip 140 is a logic chip, the first semiconductor chip 140may be, for example, a central processing unit (CPU), a controller, anapplication specific integrated circuit (ASIC) or the like. However,exemplary embodiments of the present inventive concepts are not limitedthereto.

In embodiments in which the first semiconductor chip 140 is a memorychip, the first semiconductor chip 140 may be, for example, a volatilememory chip such as a dynamic random access memory (DRAM) or a staticRAM (SRAM), or a nonvolatile memory chip such as a phase-change RAM(PRAM), a magneto resistive RAM (MRAM), a ferroelectric RAM (FeRAM), ora resistive RAM (RRAM). However, exemplary embodiments of the presentinventive concepts are not limited thereto.

The first solder ball 151 may be arranged between the firstredistribution layer 130 and the first semiconductor chip 140. Forexample, as shown in the exemplary embodiment of FIG. 1, the firstsolder ball 151 may be a plurality of discrete solder bumps that arespaced apart (e.g., in the X direction). The first solder ball 151 maybe in contact with the plurality of first wires 131 exposed on an uppersurface of the first redistribution layer 130. For example, as shown inthe exemplary embodiment of FIG. 1, a bottom surface of the first solderball 151 may directly contact a top surface of a first wire 131 locatedon the highest level of the plurality of first wires. A top surface ofthe first solder ball 151 may contact the first semiconductor chip 140.For example, in an exemplary embodiment, a top surface of the firstsolder ball 151 may be in direct contact with a conductive terminalexposed on a lower surface of the first semiconductor chip 140.

The first semiconductor chip 140 may be electrically connected with thefirst redistribution layer 130 through the first solder ball 151.However, exemplary embodiments of the present inventive concepts are notlimited thereto. For example, in other exemplary embodiments, the firstsemiconductor chip 140 may be electrically connected with the firstredistribution layer 130 through wire bonding.

In an exemplary embodiment, the first solder ball 151 may include atleast one compound selected from tin (Sn), indium (In), lead (Pb), zinc(Zn), nickel (Ni), gold (Au), silver (Ag), copper (Cu), antimony (Sb),bismuth (Bi), and a combination thereof. However, exemplary embodimentsof the present inventive concepts are not limited thereto.

The first underfill material 141 may be arranged between the firstredistribution layer 130 and the first semiconductor chip 140 (e.g., inthe Y direction). The first underfill material 141 may be arranged tosurround a side surface of the first solder ball 151 (e.g., theoutermost lateral side surfaces of the first solder ball 151 in the Xdirection).

The first underfill material 141 may be formed to further protrude froma side surface of the first semiconductor chip 140 in a lateraldirection. For example, in an exemplary embodiment, at least one of theoutermost lateral surfaces of the first underfill material extendsfarther than the first semiconductor chip 140 (e.g., in the X direction)and does not overlap with the first semiconductor chip (e.g., in the Ydirection). However, exemplary embodiments of the present inventiveconcepts are not limited thereto.

The first molding layer 145 may be arranged on the first redistributionlayer 130. For example, in an exemplary embodiment, the first moldinglayer 145 may be arranged to surround the upper surface of the firstredistribution layer 130 facing the first semiconductor chip 140, sidesurfaces of the first underfill material 141, and side surfaces of thefirst semiconductor chip 140.

Although the exemplary embodiment of FIG. 1 illustrates an upper surfaceof the first molding layer 145 and an upper surface of the firstsemiconductor chip 140 as being coplanar with each other (e.g., in the Ydirection), exemplary embodiments of the present inventive concepts arenot limited thereto. For example, in another exemplary embodiment, theupper surface of the first molding layer 145 may be arranged to coverthe upper surface of the first semiconductor chip 140 (e.g., in the Ydirection).

In an exemplary embodiment, the first molding layer 145 may include anepoxy molding compound (EMC) or two types or more of silicone hybridmaterials.

The second solder ball 152 may be arranged on a lower surface of thefirst redistribution layer 130. As shown in the exemplary embodiment ofFIG. 1, the second solder ball 152 may be a plurality of discrete solderbumps that are spaced apart (e.g., in the X direction). In an exemplaryembodiment, the discrete solder bumps of the second solder ball 152 maybe larger than the solder bumps of the first solder ball 151. However,exemplary embodiments of the present inventive concepts are not limitedthereto. As shown in the exemplary embodiment of FIG. 1, a top surfaceof the second solder ball 152 may directly contact a bottom surface ofthe first redistribution layer 130. The second solder ball 152 may be incontact with the plurality of first wires 131 exposed on the lowersurface of the first redistribution layer 130. The second solder ball152 may convexly protrude from the lower surface of the firstredistribution layer 130. The second solder ball 152 may electricallyconnect the first redistribution layer 130 to an external device. Forexample, an external device may be electrically connected to a portionof the second solder ball 152 (e.g., bottom or side surfaces) toelectrically connect the external device with the first redistributionlayer 130.

In an exemplary embodiment, the second solder ball 152 may include, forexample, at least one compound selected from tin (Sn), indium (In), lead(Pb), zinc (Zn), nickel (Ni), gold (Au), silver (Ag), copper (Cu),antimony (Sb), bismuth (Bi), and a combination thereof. However,exemplary embodiments of the present inventive concepts are not limitedthereto.

Hereinbelow, a method for fabricating a semiconductor package accordingto some exemplary embodiments will be described with reference to FIGS.1 to 8.

FIGS. 2 to 8 are cross-sectional views illustrating intermediate stagesof fabrication, provided to explain a method for fabricating asemiconductor package according to some exemplary embodiments of thepresent inventive concepts.

Referring to FIG. 2, a release layer 110 may be formed on a firstcarrier substrate 100.

In an exemplary embodiment, the first carrier substrate 100 may includeat least one material selected from silicon, metal, glass, plastic,ceramic, or the like. However, exemplary embodiments of the presentinventive concepts are not limited thereto.

The release layer 110 may be in contact with the first carrier substrate100. For example, in an exemplary embodiment, a bottom surface of therelease layer 110 may directly contact a top surface of the firstcarrier substrate 100. The release layer 110 may be conformally formedon the first carrier substrate 100. However, exemplary embodiments ofthe present inventive concepts are not limited thereto.

In an exemplary embodiment, the release layer 110 may include a samematerial as the material of the first insulation layer 133 shown inFIG. 1. For example, the release layer 110 may include a photosensitiveinsulating material, such as at least one compound selected from epoxyand polyimide. However, exemplary embodiments of the present inventiveconcepts are not limited thereto. For example, in another exemplaryembodiment, the release layer 110 may be an inorganic release layer forintroducing stable detachable characteristics. In this embodiment, therelease layer 110 may be, for example, a carbon material. However,exemplary embodiments of the present inventive concepts are not limitedthereto. The release layer may have a first etch selectivity.

Thereafter, an etch stop layer 120 may be formed on the release layer110. The etch stop layer 120 may be in contact with the release layer110. For example, a bottom surface of the etch stop layer 120 maydirectly contact a top surface of the release layer 110. The etch stoplayer 120 may be conformally formed on the release layer 110. However,exemplary embodiments of the present inventive concepts are not limitedthereto.

The etch stop layer 120 may have a second etch selectivity. The secondetch selectivity of the etch stop layer 120 may be smaller than thefirst etch selectivity of the release layer 110. Accordingly, the firstcarrier substrate 100 and the release layer 110 may be selectivelyremoved in a subsequent process.

In an exemplary embodiment, the etch stop layer 120 may include metal.For example, the etch stop layer 120 may include titanium (Ti). However,exemplary embodiments of the present inventive concepts are not limitedthereto. For example, in another exemplary embodiment, the etch stoplayer 120 may include other metal having a smaller etch selectivity thanthe etch selectivity of the release layer 110.

In an exemplary embodiment, a thickness t1 of the etch stop layer 120 inthe Y direction may be, for example, about 100 nm to about 500 nm. Forexample, the thickness t1 of the etch stop layer 120 may beapproximately about 225 nm to about 375 nm. However, exemplaryembodiments of the present inventive concepts are not limited thereto.

Referring to FIG. 3, the first redistribution layer 130 may be formed onthe etch stop layer 120. For example, a bottom surface of the firstredistribution layer 130 may directly contact a top surface of the etchstop layer 120.

The first redistribution layer 130 may include the plurality of firstwires 131, the first redistribution via 132 connecting each of theplurality of first wires 131, and the first insulation layer 133surrounding the plurality of first wires 131 and the firstredistribution via 132.

Referring to FIG. 4, the first semiconductor chip 140 may be formed onthe first redistribution layer 130. In an exemplary embodiment, thefirst semiconductor chip 140 may be, for example, a logic chip or amemory chip. The first semiconductor chip 140 may be electricallyconnected with the first redistribution layer 130 through the firstsolder ball 151.

In the exemplary embodiment of FIG. 4, the first semiconductor chip 140is electrically connected with the first redistribution layer 130through the first solder ball 151. However, exemplary embodiments of thepresent inventive concepts are not limited thereto. For example, inanother exemplary embodiment, the first semiconductor chip 140 may beelectrically connected with the first redistribution layer 130 throughwire bonding.

Referring to FIG. 5, the first underfill material 141 may be formed tosurround the side surface of the first solder ball 151 between the firstredistribution layer 130 and the first semiconductor chip 140 (e.g., theoutermost lateral side surfaces of the first solder ball 151 in the Xdirection).

The first molding layer 145 may then be formed to cover the firstsemiconductor chip 140. For example, in an exemplary embodiment, thefirst molding layer 145 may be arranged to surround the side surfaces(e.g., in the X direction) and the upper surface (e.g., in the Ydirection) of the first semiconductor chip 140, the side surfaces (e.g.,in the X direction) of the first underfill material 141, and the uppersurface (e.g., in the Y direction) of the first redistribution layer130.

The upper surface of the first semiconductor chip 140 may be exposed byetching a portion of the first molding layer 145 through a planarizationprocess. In an exemplary embodiment, the upper surface of the firstmolding layer 145 may be coplanar (e.g., in the Y direction) with theupper surface of the first semiconductor chip 140 after theplanarization process. However, exemplary embodiments of the presentinventive concepts are not limited thereto. For example, in anotherexemplary embodiment, the top surface of the first molding layer 145 maybe formed at a higher level (e.g., in the Y direction) than the topsurface of the first semiconductor chip 140 through the planarizationprocess. Therefore, the top surface of the first molding layer 145 maycover the upper surface of the first semiconductor chip 140 after theplanarization process.

Referring to FIG. 6, a second carrier substrate 160 may be formed on thefirst semiconductor chip 140 and the first molding layer 145. Forexample, as shown in the exemplary embodiment of FIG. 6, a bottomsurface of the second carrier substrate 160 may directly contact a topsurface of the semiconductor chip 140 and the first molding layer 145.In an exemplary embodiment, the second carrier substrate 160 may includeat least one material selected from silicon, metal, glass, plastic,ceramic, or the like. However, exemplary embodiments of the presentinventive concepts are not limited thereto.

Referring to FIG. 7, after the second carrier substrate 160 is formedthe device is turned upside down.

The first carrier substrate 100 and the release layer 110 may then beremoved. For example, in an exemplary embodiment, the first carriersubstrate 100 and the release layer 110 may be removed through a laserdebonding process. However, exemplary embodiments of the presentinventive concepts are not limited thereto.

In the process of removing the first carrier substrate 100 and therelease layer 110, damage to the first redistribution layer 130 may beprevented due to the etch stop layer 120 having a smaller etchselectivity than the etch selectivity of the release layer 110.

Referring to FIG. 8, the etch stop layer 120 may then be removed toexpose the first redistribution layer 130. After the etch stop layer 120is removed, the second solder ball 152 may be formed on the exposedfirst redistribution layer 130.

Referring to FIG. 1, after the second solder ball 152 is formed, thedevice may be turned upside down so that the second carrier substrate160 is disposed on the top (e.g., in the Y direction). The secondcarrier substrate 160 may then be removed.

The semiconductor package shown in FIG. 1 may then be fabricated througha sawing process.

In an exemplary embodiment, the method for fabricating the semiconductorpackage includes forming the etch stop layer 120 including metal betweenthe first carrier substrate 100 and the redistribution layer 130, suchthat the redistribution layer 130 is prevented from being damaged in thedebonding process of the first carrier substrate 100.

Hereinbelow, a method for fabricating a semiconductor package accordingto some other exemplary embodiments will be described with reference toFIGS. 9 and 10. The difference from the method for fabricating thesemiconductor package illustrated in FIGS. 1 to 8 will be highlighted.

FIGS. 9 and 10 are cross-sectional views illustrating intermediatestages of fabrication, provided to explain a method for fabricating asemiconductor package according to alternative exemplary embodiments ofthe present inventive concepts.

Referring to FIG. 9, in the method for fabricating the semiconductorpackage according to some other exemplary embodiments, the release layer110, the etch stop layer 120, and a metal layer 270 may be formed on thefirst carrier substrate 100 in sequence.

The metal layer 270 may be in contact with the etch stop layer 120. Forexample, as shown in the exemplary embodiment of FIG. 9, a bottomsurface of the metal layer 270 may directly contact a top surface of theetch stop layer 120. The metal layer 270 may be conformally formed onthe etch stop layer 120. However, exemplary embodiments of the presentinventive concepts are not limited thereto.

The metal layer 270 may include a material that is different from thematerial of the etch stop layer 120. For example, the metal layer 270may include a same material as the material of the plurality of firstwires 131 shown in FIG. 10. In an exemplary embodiment, the metal layer270 may include at least one compound selected from carbon (C), silver(Ag), cobalt (Co), tantalum (Ta), indium (In), tin (Sn), zinc (Zn),manganese (Mn), titanium (Ti), magnesium (Mg), chromium (Cr), germanium(Ge), strontium (Sr), platinum (Pt), magnesium (Mg), aluminum (Al), andzirconium (Zr).

A thickness t2 of the metal layer 270 in the second direction Y may be,for example, about 50 nm to about 350 run. However, exemplaryembodiments of the present inventive concepts are not limited thereto.

Referring to FIG. 10, the first redistribution layer 130 may be formedon the metal layer 270. For example, as shown in the exemplaryembodiment of FIG. 10, a bottom surface of the first redistributionlayer 130 may directly contact a top surface of the metal layer 270.

The first redistribution layer 130 may include the plurality of firstwires 131, the first redistribution via 132 connecting each of theplurality of first wires 131, and the first insulation layer 133surrounding the plurality of first wires 131 and the firstredistribution via 132.

In an exemplary embodiment, a wire of the plurality of first wires 131that is in contact with the metal layer 270 may be formed by using themetal layer 270 as a seed layer.

The semiconductor package illustrated in FIG. 1 may be fabricated afterthe processes illustrated in FIGS. 4 to 8 are performed.

Hereinbelow, a method for fabricating a semiconductor package accordingto some other exemplary embodiments will be described with reference toFIGS. 11 to 14. The difference from the method for fabricating thesemiconductor package illustrated in FIGS. 1 to 8 will be highlighted.

FIGS. 11 to 14 are cross-sectional views illustrating intermediatestages of fabrication, provided to explain a method for fabricating asemiconductor package according to exemplary embodiments of the presentinventive concepts.

Referring to FIG. 11, in the method for fabricating the semiconductorpackage according to some exemplary embodiments, a via 380 penetratingthrough the first molding layer 145 in the second direction Y may beformed after the processes illustrated in FIGS. 2 to 5 are performed.For example, as shown in the exemplary embodiment of FIG. 11, the via380 may include a plurality of discrete vias that extend in the Ydirection and are arranged in the X direction. The via 380 may extendfrom a top portion of the redistribution layer 130 (e.g., a top surfaceof the first wires 131) to a top surface of the first molding layer 145.As shown in the exemplary embodiment of FIG. 11, the via 380 may beformed adjacent to lateral sides of the first semiconductor chip 140(e.g., in the X direction) and are spaced apart from the firstsemiconductor chip 140 and the first underfill material 141 in adirection parallel to an upper surface of the first carrier substrate100, such as the X direction.

The via 380 may be electrically connected with the plurality of firstwires 131 exposed on the upper surface of the first redistribution layer130.

The via 380 may include a conductive material. In an exemplaryembodiment, the via 380 may include, for example, copper (Cu). Inanother exemplary embodiment, the via 380 may include at least onecompound selected from carbon (C), silver (Ag), cobalt (Co), tantalum(Ta), indium (In), tin (Sn), zinc (Zn), manganese (Mn), titanium (Ti),magnesium (Mg), chromium (Cr), germanium (Ge), strontium (Sr), platinum(Pt), magnesium (Mg), aluminum (Al), and zirconium (Zr).

Referring to FIG. 12, a second semiconductor chip 340 may be formed onthe first semiconductor chip 140. In an exemplary embodiment, the secondsemiconductor chip 340 may be a memory chip. For example, the secondsemiconductor chip 340 may be a volatile memory chip such as a dynamicrandom access memory (DRAM) or a static RAM (SRAM), or a nonvolatilememory chip such as a phase-change RAM (PRAM), a magneto resistive RAM(MRAM), a ferroelectric RAM (FeRAM), or a resistive RAM (RRAM). However,exemplary embodiments of the present inventive concepts are not limitedthereto.

A third solder ball 353 may be disposed between the via 380 and thesecond semiconductor chip 340 (e.g., in the Y direction). As shown inthe exemplary embodiment of FIG. 12, the third solder ball 353 may be aplurality of discrete solder bumps that are spaced apart (e.g., in the Xdirection). The third solder ball 353 may be in contact with the via 380exposed on the first molding layer 145. For example, as shown in theexemplary embodiment of FIG. 12, a bottom surface of the third solderball 353 may directly contact a top surface of the via and a top surfaceof the third solder ball 353 may directly contact a bottom surface ofthe second semiconductor chip. In an exemplary embodiment, the thirdsolder ball 353 may directly contact a conductive terminal exposed on alower surface of the second semiconductor chip 340.

The second semiconductor chip 340 may be electrically connected with thefirst redistribution layer 130 through the third solder ball 353 and thevia 380.

Referring to FIG. 13, a second molding layer 385 may be formed on thefirst molding layer to cover the second semiconductor chip 340.

The second molding layer 385 may be formed to surround the upper surfaceof the first molding layer 145, the upper surface of the firstsemiconductor chip 140, the third solder ball 353, and the upper, sideand bottom surfaces of the second semiconductor chip 340.

The second molding layer 385 may include, for example, epoxy moldingcompound (EMC) or two types or more of silicone hybrid materials.

The second carrier substrate 160 may then be formed on the secondmolding layer 385.

Referring to FIG. 14, a semiconductor package illustrated in FIG. 14 maybe fabricated after the processes illustrated in FIGS. 7 and 8 areperformed in sequence.

For example, after the second carrier substrate 160 is formed, thedevice may be turned upside down. The first carrier substrate 100, therelease layer 110, and the etch stop layer 120 may then be removed andthe second solder ban 152 may then be formed on the first redistributionlayer 130.

The device may then be turned upside down and the second carriersubstrate 160 may then be removed. The semiconductor package illustratedin FIG. 14 may then be fabricated through a sawing process.

Hereinbelow, a method for fabricating a semiconductor package accordingto some other exemplary embodiments of the present inventive conceptswill be described with reference to FIGS. 15 to 18. The difference fromthe method for fabricating the semiconductor package illustrated inFIGS. 1 to 8 will be highlighted.

FIGS. 15 to 18 are cross-sectional views illustrating intermediatestages of fabrication, provided to explain a method for fabricating asemiconductor package according to some other exemplary embodiments.

Referring to FIG. 15, in the method for fabricating the semiconductorpackage according to some other exemplary embodiments, a via 480penetrating through the first molding layer 145 in the second directionY may be formed after the processes illustrated in FIGS. 2 to 5 areperformed. As shown in the exemplary embodiment of FIG. 15, the via 480may be formed on lateral sides of the first semiconductor chip 140(e.g., in the X direction) and are spaced apart from the firstsemiconductor chip 140 and the first underfill material 141 in the Xdirection.

A second redistribution layer 490 may then be formed on the firstsemiconductor chip 140, the first molding layer 145, and the via 480.

The second redistribution layer 490 may include a plurality of secondwires 491, a second redistribution via 492 connecting each of theplurality of second wires 491, and a second insulation layer 493surrounding the plurality of second wires 491 and the secondredistribution via 492. While the second wires 491 shown in theexemplary embodiment of FIG. 15 include horizontally arranged secondwires 491 that are formed on two levels (e.g., in the Y direction),exemplary embodiments of the present inventive concepts are not limitedthereto. For example, in other exemplary embodiments, the second wires491 may be formed on three or more levels. The plurality of second wires491 exposed on a lower surface of the second redistribution layer 490may be electrically connected with the via 480. For example, a bottomsurface of the second wires 491 may contact a top surface of the via480.

Referring to FIG. 16, a second semiconductor chip 440 may be formed onthe second redistribution layer 490. In an exemplary embodiment, thesecond semiconductor chip 440 may be a memory chip.

A third solder ball 453 may be formed between the second redistributionlayer 490 and the second semiconductor chip 440 (e.g., in the Ydirection). For example, a bottom surface of the third solder ball 453may contact a top surface of second redistribution layer 490 and a topsurface of the third solder ball 453 may contact a bottom surface of thesecond semiconductor chip 440. In an exemplary embodiment, the thirdsolder ball 453 may be in contact with a conductive terminal exposed onthe second redistribution layer 490. The third solder ball 453 may alsobe in contact with a conductive terminal exposed on a lower surface ofthe second semiconductor chip 440.

The second semiconductor chip 440 may be electrically connected with thefirst redistribution layer 130 through the third solder ball 453, thesecond redistribution layer 490, and the via 480.

Referring to FIG. 17, a second molding layer 485 may be formed on thesecond redistribution layer 490 to cover the second semiconductor chip440.

The second molding layer 485 may be formed to surround the upper surfaceof the second redistribution layer 490, the third solder ball 453, andthe upper surface and side surfaces of the second semiconductor chip440.

In an exemplary embodiment, the second molding layer 485 may includeepoxy molding compound (EMC) or two types or more of silicone hybridmaterials. However, exemplary embodiments of the present inventiveconcepts are not limited thereto.

The second carrier substrate 160 may then be formed on the secondmolding layer 485.

Referring to FIG. 18, a semiconductor package illustrated in FIG. 18 maybe fabricated after the processes illustrated in FIGS. 7 and 8 areperformed in sequence.

For example, after the second carrier substrate 160 is formed, thedevice is turned upside down.

The first carrier substrate 100, the release layer 110, and the etchstop layer 120 may then be removed and the second solder ball 152 may beformed on the first redistribution layer 130. The device may then beturned upside down and the second carrier substrate 160 may then beremoved. The semiconductor package illustrated in FIG. 18 may then befabricated through a sawing process.

Hereinafter, a method for fabricating a semiconductor package accordingto some other exemplary embodiments will be described with reference toFIG. 19. The difference from the method for fabricating thesemiconductor package illustrated in FIGS. 1 to 8 will be highlighted.

FIG. 19 is a cross-sectional view provided to explain a semiconductorpackage fabricated by a method for fabricating a semiconductor packageaccording to some other exemplary embodiments of the present inventiveconcepts.

Referring to FIG. 19, in the method for fabricating the semiconductorpackage according to some other exemplary embodiments, a second package20 may be formed on a first package 10 after the processes illustratedin FIGS. 2 to 5, FIG. 11, and FIGS. 6 to 8, and FIG. 1 are performed insequence.

In an exemplary embodiment, the second package 20 may include asubstrate 21, a second semiconductor chip 22, a fourth solder ball 23, asecond underfill material 24, and a second molding layer 25.

In an exemplary embodiment, the substrate 21 may be a printed circuitboard (PCB) or a ceramic substrate. Further, the substrate 21 may be aninterposer. However, exemplary embodiments of the present inventiveconcepts are not limited thereto.

In an exemplary embodiment, the second semiconductor chip 22 may be amemory chip. The fourth solder ball 23 may be formed between thesubstrate 21 and the second semiconductor chip 22 (e.g., in the Ydirection). For example, as shown in the exemplary embodiment of FIG.19, the fourth solder ball 23 may be a plurality of discrete solderbumps that are spaced apart (e.g., in the X direction). As shown in theexemplary embodiment of FIG. 19, a bottom surface of the fourth solderball 23 may contact a top surface of the substrate 21 and a top surfaceof the fourth solder ball 23 may contact a bottom surface of the secondsemiconductor chip 22. For example, in an exemplary embodiment, a bottomsurface of the fourth solder ball 23 may be in contact with a conductiveterminal exposed on the substrate 21. A top surface of the fourth solderball 23 may be in contact with a conductive socket arranged on a lowersurface of the second semiconductor chip 22.

The second underfill material 24 may be formed to surround a sidesurface of the fourth solder ball 23 between the substrate 21 and thesecond semiconductor chip 22 (e.g., the outermost lateral side surfacesof the fourth solder ball 23 in the X direction). The second moldinglayer 25 may be formed to surround an upper surface of the substrate 21facing the second semiconductor chip 22, side surfaces of the secondunderfill material 24, and the upper surface and side surfaces of thesecond semiconductor chip 22.

A third solder ball 553 may be formed between a via 580 and thesubstrate 21 (e.g., in the Y direction). The third solder ball 553(e.g., a bottom surface in the Y direction) may be in contact with thevia 580 exposed on the first molding layer 145. In addition, the thirdsolder ball 553 may be in contact with a lower surface of the substrate21, such as a conductive terminal exposed on a lower surface of thesubstrate 21.

The second package 20 may be electrically connected with the firstpackage 10 through the third solder ball 553 and the via 580.

Hereinbelow, a method for fabricating a semiconductor package accordingto some other exemplary embodiments of the present inventive conceptswill be described with reference to FIG. 20. The difference from themethod for fabricating the semiconductor package illustrated in FIGS. 1to 8 will be highlighted.

FIG. 20 is a cross-sectional view provided to explain a semiconductorpackage fabricated by a method for fabricating a semiconductor packageaccording to some other exemplary embodiments.

Referring to FIG. 20, in the method for fabricating the semiconductorpackage according to some other exemplary embodiments of the presentinventive concepts, the second package 20 may be formed on a secondredistribution layer 690 after the processes illustrated in FIGS. 2 to5, FIG. 15, and FIGS. 6 to 8, and FIG. 1 are performed.

The second redistribution layer 690 may include a plurality of secondwires 691, a second redistribution via 692 connecting each of theplurality of second wires 691, and a second insulation layer 693surrounding the plurality of second wires 691 and the secondredistribution via 692. While the second wires 691 shown in theexemplary embodiment of FIG. 20 include horizontally arranged secondwires 691 that are formed on two levels (e.g., in the Y direction),exemplary embodiments of the present inventive concepts are not limitedthereto. For example, in other exemplary embodiments, the second wires691 may be formed on three or more levels.

The second package 20 may include the substrate 21, the secondsemiconductor chip 22, the fourth solder ball 23, the second underfillmaterial 24, and the second molding layer 25.

In an exemplary embodiment, the second semiconductor chip 22 may be amemory chip. The fourth solder ball 23 may be formed between thesubstrate 21 and the second semiconductor chip 22 (e.g., in the Ydirection). As shown in the exemplary embodiment of FIG. 20, a bottomsurface of the fourth solder ball 23 may contact a top surface of thesubstrate 21 and a top surface of the fourth solder ball 23 may contacta bottom surface of the second semiconductor chip 22. In an exemplaryembodiment, the bottom surface of the fourth solder ball 23 may contacta conductive terminal exposed on the top surface of the substrate 21 anda top surface of the fourth solder ball 23 may contact a conductiveterminal exposed on a lower surface of the second semiconductor chip 22.

The second underfill material 24 may be formed to surround a sidesurface of the fourth solder ball 23 between the substrate 21 and thesecond semiconductor chip 22 (e.g., the outermost lateral side surfacesof the fourth solder ball 23 in the X direction). The second moldinglayer 25 may be formed to surround the upper surface of the substrate 21facing the second semiconductor chip 22, the side surfaces of the secondunderfill material 24, and the upper surface, side surfaces and lowersurface of the second semiconductor chip 22.

A third solder ball 653 may be formed between the second redistributionlayer 690 and the substrate 21 (e.g., in the Y direction). As shown inthe exemplary embodiment of FIG. 20, a top surface of the third solderball 653 may contact a bottom surface of the substrate 21 and a bottomsurface of the third solder ball 653 may contact a top surface of thesecond redistribution layer. For example, in an exemplary embodiment,the bottom surface of the third solder ball 653 may contact a conductiveterminal exposed on the second redistribution layer 690 and the topsurface of the third solder ball 653 may contact a conductive terminalexposed on a lower surface of the substrate 21.

The second package 20 may be electrically connected with the firstpackage 10 through the third solder ball 653, the second redistributionlayer 690, and the via 680.

Exemplary embodiments according to the present inventive concepts wereexplained hereinabove with reference to the drawings attached, but itshould be understood that the present inventive concepts are not limitedto the aforementioned exemplary embodiments, but may be fabricated invarious different forms, and may be implemented by a person skilled inthe art in other specific forms without altering the technical conceptor essential characteristics of the present inventive concepts.Accordingly, it will be understood that the exemplary embodimentsdescribed above are only illustrative and should not be construed aslimiting.

What is claimed is:
 1. A method for fabricating a semiconductor package,the method comprising: forming a release layer on a first carriersubstrate; forming an etch stop layer on the release layer; forming afirst redistribution layer on the etch stop layer, the firstredistribution layer comprising a plurality of first wires and a firstinsulation layer surrounding the plurality of first wires; forming afirst semiconductor chip on the first redistribution layer; forming asolder ball between the first redistribution layer and the firstsemiconductor chip; forming a second carrier substrate on the firstsemiconductor chip; removing the first carrier substrate, the releaselayer, and the etch stop layer; and removing the second carriersubstrate.
 2. The method of claim 1, wherein: the release layer has afirst etch selectivity; the etch stop layer has a second etchselectivity that is smaller than the first etch selectivity; and theetch stop layer comprises metal.
 3. The method of claim 2, wherein theetch stop layer comprises Ti.
 4. The method of claim 1, furthercomprising: forming a metal layer on the etch stop layer, the metallayer comprising a material that is different from a material of theetch stop layer.
 5. The method of claim 4, wherein the metal layer andthe plurality of first wires comprise a same material.
 6. The method ofclaim 1, wherein the release layer and the first insulation layercomprise a same material.
 7. The method of claim 1, wherein a thicknessof the etch stop layer is in a range of about 100 nm to about 500 nm. 8.The method of claim 1, further comprising: forming a secondsemiconductor chip on the first semiconductor chip, wherein the secondcarrier substrate is formed on the second semiconductor chip.
 9. Themethod of claim 8, further comprising: forming a via adjacent to thefirst semiconductor chip and spaced apart from the first semiconductorchip in a direction of a top surface of the first carrier substrate;wherein the second semiconductor chip is connected to the via.
 10. Themethod of claim 1, further comprising: forming a second redistributionlayer on the first semiconductor chip, the second redistribution layercomprising a plurality of second wires and a second insulation layersurrounding the plurality of second wires.
 11. The method of claim 10,further comprising: forming a second semiconductor chip on the secondredistribution layer, wherein the second carrier substrate is formed onthe second semiconductor chip.
 12. A method for fabricating asemiconductor package, the method comprising: forming a release layer ona first carrier substrate; forming an etch stop layer comprising metalon the release layer; forming a first redistribution layer on the etchstop layer, the first redistribution layer comprising a plurality offirst wires and a first insulation layer surrounding the plurality offirst wires; forming a first semiconductor chip on the firstredistribution layer; forming a solder ball between the firstredistribution layer and the first semiconductor chip; forming a moldinglayer that covers the first semiconductor chip; and removing the firstcarrier substrate, the release layer, and the etch stop layer, whereinthe release layer and the first insulation layer comprise a samematerial.
 13. The method of claim 12, wherein the etch stop layercomprises Ti.
 14. The method of claim 12, further comprising: forming ametal layer on the etch stop layer, the metal layer comprising amaterial that is different from a material of the etch stop layer. 15.The method of claim 14, wherein the metal layer and the plurality offirst wires comprise a same material.
 16. The method of claim 14,wherein a thickness of the metal layer is in a range of about 50 nm toabout 350 nm.
 17. The method of claim 12, further comprising: forming asecond semiconductor chip on the first semiconductor chip.
 18. A methodfor fabricating a semiconductor package, the method comprising: forminga release layer on a first carrier substrate; forming an etch stop layercomprising metal on the release layer; forming a first redistributionlayer on the etch stop layer, the first redistribution layer comprisinga plurality of first wires and a first insulation layer surrounding theplurality of first wires; forming a first semiconductor chip on thefirst redistribution layer; forming a solder ball between the firstredistribution layer and the first semiconductor chip; forming a moldinglayer that covers the first semiconductor chip; forming a second carriersubstrate on the molding layer; and removing the first carriersubstrate, the release layer, and the etch stop layer; and removing thesecond carrier substrate, wherein the release layer and the firstinsulation layer comprise a same material.
 19. The method of claim 18,wherein the etch stop layer comprises Ti.
 20. The method of claim 18,wherein a thickness of the etch stop layer is about 100 nm to about 500nm.